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M48T58 M48T58Y
5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER(R) SRAM
Features

Integrated, ultra low power SRAM, real time clock, power-fail control circuit and battery BYTEWIDETM RAM-like clock access BCD coded year, month, day, date, hours, minutes, and seconds Frequency test output for real time clock Automatic power-fail chip deselect and write protection Write protect voltages (VPFD = power-fail deselect voltage): - M48T58: VCC = 4.75 to 5.5V 4.5V VPFD 4.75V - M48T58Y: VCC = 4.5 to 5.5V 4.2V VPFD 4.5V
28 1
PCDIP28 (PC) Battery/Crystal CAPHAT
SNAPHAT (SH) Battery/Crystal

Self-contained battery and crystal in the CAPHATTM dip package Packaging includes a 28-lead SOIC and SNAPHAT(R) top (to be ordered separately) SOIC package provides direct connection for a snaphat housing containing the battery and crystal Pin and function compatible with JEDEC standard 8 Kb x8 SRAMs RoHS compliant - Lead-free second level interconnect
28 1

SOH28 (MH)
August 2007
Rev 5
1/31
www.st.com 1
Contents
M48T58, M48T58Y
Contents
1 2 3 4 5 6 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 6.2 6.3 6.4 6.5 6.6 6.7 Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Calibrating the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Battery low flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 8 9 10 11
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
M48T58, M48T58Y
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCDIP28 - 28-pin plastic DIP, battery CAPHAT, package mechanical data . . . . . . . . . . . 24 SOH28 - 28-lead plastic small outline, 4-socket battery SNAPHAT, package mech. data 25 SH - 4-pin SNAPHAT housing for 48mAh battery & crystal, package mech. data. . . . . . . 26 SH - 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data. . . . . . 27 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
List of figures
M48T58, M48T58Y
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write enable controlled, write AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chip enable controlled, write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PCDIP28 - 28-pin plastic DIP, battery CAPHAT, package outline . . . . . . . . . . . . . . . . . . . 24 SOH28 - 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline . . . . 25 SH - 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline . . . . . . . . . . 26 SH - 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline . . . . . . . . . 27
4/31
M48T58, M48T58Y
Summary description
1
Summary description
The M48T58/Y TIMEKEEPER(R) RAM is a 8Kb x 8 non-volatile static RAM and real time clock. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution. The M48T58/Y is a non-volatile pin and function equivalent to any JEDEC standard 8Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 28-pin, 600mil DIP CAPHATTM houses the M48T58/Y silicon with a quartz crystal and a long life lithium button cell in a single package. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT(R) housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is "M4T28BR12SH" (see Table 17 on page 29). Figure 1. Logic diagram
VCC
13 A0-A12
8 DQ0-DQ7
W E1 E2 G M48T58 M48T58Y FT
VSS
AI01374B
5/31
Summary description Table 1. Signal names
A0-A12 DQ0-DQ7 FT E1 E2 G W VCC VSS Address Inputs Data Inputs / Outputs Frequency Test Output (Open Drain) Chip Enable 1 Chip Enable 2 Output Enable WRITE Enable Supply Voltage Ground
M48T58, M48T58Y
Figure 2.
DIP connections
FT A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 M48T58 22 8 M48T58Y 21 9 20 10 19 11 18 12 17 13 16 14 15
AI01375B
VCC W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3
Figure 3.
SOIC connections
FT A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 28 1 2 27 3 26 4 25 5 24 6 23 7 22 M48T58Y 8 21 9 20 10 19 11 18 12 17 13 16 14 15
AI01376B
VCC W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3
6/31
M48T58, M48T58Y Figure 4. Block diagram
Summary description
FT
OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL POWER
8 x 8 BiPORT SRAM ARRAY
A0-A12
8184 x 8 SRAM ARRAY LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD
DQ0-DQ7
E1 E2 W G
VCC
VSS
AI01377C
7/31
Operation modes
M48T58, M48T58Y
2
Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz controlled clock oscillator of the M48T58/Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDETM clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour BCD format (except for the century). Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORTTM READ/write memory cells. The M48T58/Y includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T58/Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out-of-tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns. Table 2.
Mode Deselect Deselect WRITE READ READ Deselect Deselect VSO to VPFD (min)(1) VSO(1) 4.75 to 5.5V or 4.5 to 5.5V
Operating modes
VCC E1 VIH X VIL VIL VIL X X E2 X VIL VIH VIH VIH X X G X X X VIL VIH X X W X X VIL VIH VIH X X DQ0-DQ7 High Z High Z DIN DOUT High Z High Z High Z Power Standby Standby Active Active Active CMOS Standby Battery Back-up Mode
1. See Table 11 on page 23 for details.
Note:
X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
8/31
M48T58, M48T58Y
Read mode
3
Read mode
The M48T58/Y is in the READ Mode whenever W (WRITE Enable) is high, E1 (Chip Enable 1) is low, and E2 (Chip Enable 2) is high. The unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E1, E2, and G access times are also satisfied. If the E1, E2 and G access times are not met, valid data will be available after the latter of the Chip Enable Access times (tE1LQV or tE2HQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E1, E2 and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E1, E2 and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
Figure 5.
Read mode AC waveforms
tAVAV A0-A12 tAVQV tE1LQV E1 tE1LQX tE2HQV E2 tE2HQX tGLQV G tGLQX DQ0-DQ7 VALID
AI00962
VALID tAXQX tE1HQZ
tE2LQZ
tGHQZ
Note:
WRITE Enable (W) = High.
9/31
Read mode Table 3.
Symbol tAVAV tAVQV tE1LQV tE2HQV tGLQV tE1LQX(2) tE2HQX(2) tGLQX(2) tE1HQZ(2) tE2LQZ(2) tGHQZ(2) tAXQX
M48T58, M48T58Y Read mode AC characteristics
Parameter(1) READ Cycle Time Address Valid to Output Valid Chip Enable 1 Low to Output Valid Chip Enable 2 High to Output Valid Output Enable Low to Output Valid Chip Enable 1 Low to Output Transition Chip Enable 2 High to Output Transition Output Enable Low to Output Transition Chip Enable 1 High to Output Hi-Z Chip Enable 2 Low to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition 10 5 5 5 25 25 25 70 70 70 70 35 M48T58/Y Unit Min Max ns ns ns ns ns ns ns ns ns ns ns ns
1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 5pF.
10/31
M48T58, M48T58Y
Write mode
4
Write mode
The M48T58/Y is in the WRITE Mode whenever W and E1 are low and E2 is high. The start of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2. The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low for a minimum of tE1HAX or tE2LAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E1 and G and a high on E2, a low on W will disable the outputs tWLQZ after W falls.
Figure 6.
Write enable controlled, write AC waveform
tAVAV A0-A12 VALID tAVWH tAVE1L E1 tAVE2H E2 tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI00963
tWHAX
tWHQX
11/31
Write mode Figure 7. Chip enable controlled, write AC waveforms
tAVAV A0-A12 VALID tAVE1H tAVE1L E1 tE1LE1H
M48T58, M48T58Y
tE1HAX
tAVE2L tAVE2H E2 tAVWL W tE1HDX tE2LDX DQ0-DQ7 DATA INPUT tDVE1H tDVE2L tE2HE2L tE2LAX
AI00964B
12/31
M48T58, M48T58Y Table 4.
Symbol tAVAV tAVWL tAVE1L tAVE2H tWLWH tE1LE1H tE2HE2L tWHAX tE1HAX tE2LAX tDVWH tDVE1H tDVE2L tWHDX tE1HDX tE2LDX tWLQZ(2)(3) tAVWH tAVE1H tAVE2L tWHQX(2)(3)
Write mode Write mode AC characteristics
Parameter(1) WRITE Cycle Time Address Valid to WRITE Enable Low Address Valid to Chip Enable 1 Low Address Valid to Chip Enable 2 High WRITE Enable Pulse Width Chip Enable 1 Low to Chip Enable 1 High Chip Enable 2 High to Chip Enable 2 Low WRITE Enable High to Address Transition Chip Enable 1 High to Address Transition Chip Enable 2 Low to Address Transition Input Valid to WRITE Enable High Input Valid to Chip Enable 1 High Input Valid to Chip Enable 2 Low WRITE Enable High to Input Transition Chip Enable 1 High to Input Transition Chip Enable 2 Low to Input Transition Write Enable Low to Output Hi-Z Address Valid to WRITE Enable High Address Valid to Chip Enable 1 High Address Valid to Chip Enable 2 Low WRITE Enable High to Output Transition 60 60 60 5 70 0 0 0 50 55 55 0 0 0 30 30 30 5 5 5 25 M48T58/Y Unit Min Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 5pF. 3. If E1 goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance state.
13/31
Data retention mode
M48T58, M48T58Y
5
Data retention mode
With valid VCC applied, the M48T58/Y operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as "don't care."
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T58/Y may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T58/Y for an accumulated period of at least 7 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus trec (min). E1 should be kept high or E2 low as VCC rises past VPFD (min) to prevent inadvertent WRITE cycles prior to system stabilization. Normal RAM operation can resume trec after VCC exceeds VPFD (max). For more information on Battery Storage Life refer to the Application Note AN1012.
14/31
M48T58, M48T58Y
Clock operations
6
6.1
Clock operations
Reading the clock
Updates to the TIMEKEEPER(R) registers (see Table 5) should be halted before clock data is read to prevent reading data in transition. The BiPORTTM TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ Bit, D6 in the Control Register 1FF8h. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.'
6.2
Setting the clock
Bit D7 of the Control register (1FF8h) is the WRITE Bit. Setting the WRITE Bit to a '1,' like the READ Bit, halts updates to the TIMEKEEPER(R) registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 5). Resetting the WRITE Bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. The bits marked as '0' in Table 5 on page 16 must be written to '0' to allow for normal TIMEKEEPER and RAM operation. After the WRITE Bit is reset, the next clock update will occur within one second. See the Application Note AN923 "TIMEKEEPER Rolling Into the 21st Century" for information on Century Rollover.
6.3
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T58/Y is shipped from STMicroelectronics with the STOP Bit set to a '1.' When reset to a '0,' the M48T58/Y oscillator starts within 1 second.
15/31
Clock operations Table 5.
Address D7 1FFFh 1FFEh 1FFDh 1FFCh 1FFBh 1FFAh 1FF9h 1FF8h 0 BLE 0 0 0 ST W R D6 D5 D4 D3 D2 D1 Year 10 M Month Date 0 Day Hours Minutes Seconds Calibration D0 10 Years 0 BL FT 0 0
M48T58, M48T58Y Register map
Data Function/Range BCD Format Year Month Date Century/Day Hours Minutes Seconds Control 00-99 01-12 01-31 0-1/1-7 00-23 00-59 00-59
10 Date CEB CB
10 Hours 10 Minutes 10 Seconds S
Keys: S = SIGN Bit FT = FREQUENCY TEST Bit R = READ Bit W = WRITE Bit ST = STOP Bit 0 = Must be set to '0' BLE = Battery Low Enable Bit BL = Battery Low Bit (Read only) CEB = Century Enable Bit CB = Century Bit Note: When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set). When CEB is set to '0,' CB will not toggle. The WRITE Bit does not need to be set to write to CEB.
6.4
Calibrating the Clock
The M48T58/Y is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T58/Y improves to better than +1/-2 ppm at 25C. The oscillation rate of any crystal changes with temperature (see Figure 8 on page 18). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome "trim" capacitors. The M48T58/Y design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 9 on page 18. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Byte occupies the five lower order bits (D4-D0) in the Control Register 1FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit
16/31
M48T58, M48T58Y
Clock operations
D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration Byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or - 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T58/Y may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the Calibration Byte. The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the Frequency Test (FT) Bit (D6 in the Day Register) is set to a '1,' and D7 of the Seconds Register is a '0' (Oscillator Running), The Frequency Test (Pin 1) will toggle at 512Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (WR001010) to be loaded into the Calibration Byte for correction. The Frequency Test pin is an open drain output which requires a pull-up resistor for proper operation. A 500-10k resistor is recommended in order to control the rise time. For more information on calibration, see Application Note AN934, "TIMEKEEPER(R) Calibration."
17/31
Clock operations Figure 8. Crystal accuracy across temperature
ppm 20
M48T58, M48T58Y
0
-20
-40 F = -0.038 ppm (T - T )2 10% 0 F C2 T0 = 25 C -80
-60
-100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 C
AI02124
Figure 9.
Clock calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
6.5
Battery low flag
The M48T58/Y automatically performs periodic battery voltage monitoring upon power-up. The Battery Low flag (BL), Bit D6 of the flags Register 1FFDh, will be asserted high if the internal or SNAPHAT(R) battery is found to be less than approximately 2.5V and the Battery Low Enable (BLE) Bit has been previously set to '1.' The BL flag will remain active until completion of battery replacement and subsequent battery low monitoring tests. If a battery low is generated during a power-up sequence, this indicates that the battery voltage is below 2.5V (approximately), which may be insufficient to maintain data integrity. Data should be considered suspect and verified as correct. A fresh battery should be installed. The SNAPHAT top may be replaced while VCC is applied to the device.
18/31
M48T58, M48T58Y Note: Note:
Clock operations
This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is disconnected. Battery monitoring is a useful technique only when performed periodically. The M48T58/Y only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
6.6
Century bit
Bit D5 and D4 of Clock Register 1FFCh contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle.
Note:
The WRITE Bit must be set in order to write to the CENTURY Bit.
6.7
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A bypass capacitor value of 0.1F (as shown in Figure 10) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 10. Supply voltage protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
19/31
Maximum rating
M48T58, M48T58Y
7
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6.
Symbol TA TSTG VIO VCC IO PD
Absolute maximum ratings
Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Input or Output Voltages Supply Voltage Output Current Power Dissipation Value 0 to 70 -40 to 85 260 -0.3 to 7 -0.3 to 7 20 1 Unit C C C V V mA W
TSLD(1)(2)(3) Lead Solder Temperature for 10 seconds
1. For DIP package: Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). 2. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225C (total thermal budget not to exceed 180C for between 90 to 150 seconds). 3. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
Caution: Caution:
Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
20/31
M48T58, M48T58Y
DC and AC parameters
8
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in Table 7. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7. Operating and AC measurement conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages M48T58 4.75 to 5.5 0 to 70 100 5 0 to 3 1.5 M48T58Y 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5 Unit V C pF ns V V
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 11. AC measurement load circuit
5V
1.9k DEVICE UNDER TEST 1k
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
AI01030
Table 8.
Symbol CIN COUT
(3)
Capacitance
Parameter(1)(2) Input Capacitance Output Capacitance Min Max 10 10 Unit pF pF
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
21/31
DC and AC parameters Table 9.
Symbol ILI ILO(2) ICC ICC1 ICC2 VIL VIH VOL VOH
M48T58, M48T58Y
DC characteristics
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage (FT)(3) IOL = 2.1mA IOL = 10mA IOH = -1mA 2.4 Test condition(1) Min 0V VIN VCC 0V VOUT VCC Outputs open E1 = VIH E2 = VIO E1 = VCC - 0.2V E2 = VSS + 0.2V -0.3 2.2 M48T58 Max 1 1 50 3 3 0.8 VCC + 0.3 0.4 0.4 2.4 -0.3 2.2 M48T58Y Unit Min Max 1 1 50 3 3 0.8 VCC + 0.3 0.4 0.4 V V A A mA mA mA V V
1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. Outputs deselected. 3. The FT pin is Open Drain.
Figure 12. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tPD INPUTS
RECOGNIZED
tR tRB tDR DON'T CARE trec
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01168C
22/31
M48T58, M48T58Y Table 10.
Symbol tPD tF(2) tFB(3) tR tRB trec
DC and AC parameters Power down/up AC characteristics
Parameter(1) E1 or W at VIH or E2 at VIL before Power Down VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time VPFD (max) to Inputs Recognized M48T58 M48T58Y Min 0 300 10 10 10 1 40 200 Max Unit s s s s s s ms
1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 11.
Symbol VPFD VSO tDR(3)
Power down/up trip points DC characteristics
Parameter(1)(2) Power-fail Deselect Voltage M48T58 M48T58Y Min 4.5 4.2 Typ 4.6 4.35 3.0 7 Max 4.75 4.5 Unit V V V YEARS
Battery Back-up Switchover Voltage Expected Data Retention Time
1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. All voltages referenced to VSS. 3. At 25C, VCC = 0V.
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Package mechanical data
M48T58, M48T58Y
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 13. PCDIP28 - 28-pin plastic DIP, battery CAPHAT, package outline
A2
A
A1 B1 B e3 D
N
L eA
C
e1
E
1 PCDIP
Note:
Drawing is not to scale. Table 12.
Symb Typ A A1 A2 B B1 C D E e1 e3 eA L N Min 8.89 0.38 8.38 0.38 1.14 0.20 39.37 17.83 2.29 29.72 15.24 3.05 28 Max 9.65 0.76 8.89 0.53 1.78 0.31 39.88 18.34 2.79 36.32 16.00 3.81 Typ Min 0.350 0.015 0.330 0.015 0.045 0.008 1.550 0.702 0.090 1.170 0.600 0.120 28 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.570 0.722 0.110 1.430 0.630 0.150
PCDIP28 - 28-pin plastic DIP, battery CAPHAT, package mechanical data
mm inches
24/31
M48T58, M48T58Y
Package mechanical data
Figure 14. SOH28 - 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Note:
Drawing is not to scale. Table 13. SOH28 - 28-lead plastic small outline, 4-socket battery SNAPHAT, package mech. data
mm Symb Typ A A1 A2 B C D E e eB H L a N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inches
25/31
Package mechanical data
M48T58, M48T58Y
Figure 15. SH - 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note:
Drawing is not to scale. Table 14. SH - 4-pin SNAPHAT housing for 48mAh battery & crystal, package mech. data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inches
26/31
M48T58, M48T58Y
Package mechanical data
Figure 16. SH - 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note:
Drawing is not to scale. Table 15. SH - 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data
mm Symb Typ A A1 A2 A3 B D E eB L 0.46 21.21 17.27 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 3.61 2.29 0.018 0.835 0.680 0.126 0.080 0.315 0.285 Typ Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.142 0.090 inches
27/31
Part numbering
M48T58, M48T58Y
10
Part numbering
Table 16.
Example: Device type M48T Supply voltage and write protect voltage 58(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 58Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V Speed -70 = 70ns Package PC = PCDIP28 MH(2) = SOH28 Temperature range 1 = 0 to 70C Shipping method For SOH28: blank = Tubes (Not for New Design - Use E) E = Lead-free Package (ECOPACK), Tubes F = Lead-free Package (ECOPACK), Tape & Reel TR = Tape & Reel (Not for New Design - Use F) For PCDIP28: blank = Tubes
1. The M48T58 part is offered with the PCDIP28 (e.g., CAPHATTM) package only. 2. The SOIC package (SOH28) requires the SNAPHAT(R) battery package which is ordered separately under the part number "M4TXX-BR12SH" in plastic tube or "M4TXX-BR12SHTR" in Tape & Reel form (see Table 17).
Ordering information scheme
M48T 58 -70 MH 1 E
Caution:
Do not place the SNAPHAT battery package "M4TXX-BR12SH" in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
28/31
M48T58, M48T58Y Table 17. SNAPHAT battery table
Description Lithium Battery (48mAh) SNAPHAT Lithium Battery (120mAh) SNAPHAT
Part numbering
Part Number M4T28-BR12SH M4T32-BR12SH
Package SH SH
29/31
Revision history
M48T58, M48T58Y
11
Revision history
Table 18.
Date Jul-1999 27-Jul-2000 04-Jun-2001 31-Jul-2001 20-May-2002 01-Apr-2003 17-Jul-2003 02-Apr-2004 30-Aug-2007
Document revision history
Revision 1.0 1.1 2.0 2.1 2.2 3.0 3.1 4.0 5.0 First Issue Century Bit and Battery Low Flag Paragraphs added; Power Down/Up AC Characteristics Table and Waveforms changed (Table 10, Figure 12) Reformatted; temperature information added (Table 9, 3, 4, 10, 11) Formatting changes from recent document review findings Modify reflow time and temperature footnotes (Table 6) v2.2 template applied; test condition updated (Table 11) Update "Battery Low Flag" information Reformatted; update Lead-free packaging information (Table 6, 16) Reformatted; added lead-free second level interconnect information to cover page and Section 9: Package mechanical data; updated Table 9. Changes
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M48T58, M48T58Y
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